Architectural design of a reconfigurable and extensible VLIW processor

ρ-VEX is a reconfigurable and extensible Very-Long Instruction Word (VLIW) processor. It is part of the overall “Liquid Architectures” research theme within the Computer Engineering Lab at TU Delft, The Netherlands. The ρ-VEX processor architecture is based on the VEX ISA. The main concept of our design is to be able to dynamically adapt the hardware design to match requirements from the applications and the operating environment. In this manner, resource utilization can be improved for energy savings or increased performance, e.g., by executing additional programs on the “freed” resources. Consequently, our design can be seen as a wide-issue (up to 8) VLIW processor or as several 2-issue VLIW cores. Our designs have been used in several courses given at TU Delft, and we can make this material available for professors at other institutes upon request. (Note: When referring to ρ-VEX, use the greek letter or use “rVEX” when only roman letter are available.)

Getting started

Read how to get started with the current release of the ρ-VEX processor.


You can find releases and other files here.


Read how to get in touch with us, to get more information about the processor or the project in general, or to discuss possibilities for collaboration.