What is the ρ-VEX?
The ρ-VEX is a reconfigurable and extensible VLIW processor.
- VLIW: this stands for “very-long instruction word”. It implies that the processor can issue multiple instructions in parallel, and that the selection of which instructions are to run in parallel is done at compile-time. It is called such because each instruction word has to describe multiple independent instructions.
- Reconfigurable: the ρ-VEX can constantly adapt to the available instruction-level parallelism (ILP) and thread-level parallelism (TLP) to make the best use of the available computational resources. It can do so by dynamically changing the mapping between the available threads and issue slots. Thus, it can behave as many small VLIW processors when a lot of TLP is available, or as one large processor when a lot of ILP is available. Note that this is not FPGA reconfiguration: all resources needed to do the switching are inferred from the hardware description. This allows the ρ-VEX to be implemented in any technology, and limits the overhead of a reconfiguration to a mere pipeline flush: in the order of 5 cycles!
- Extensible: the ρ-VEX is designed to make it easy to add or modify instructions and control registers. Simple enough to let students do it as part of a short lab course!
The ρ-VEX is part of the overall “Liquid Architectures” research theme within the Computer Engineering Lab at TU Delft, The Netherlands. The instruction-set architecture is based on VEX; the example architecture from the book “Embedded Computing” by Joseph A. Fisher, Paolo Faraboschi, and Cliff Young.
Why did we make the ρ-VEX?
Dynamic workloads call for a dynamic processor.
- Dynamic workloads: modern embedded workloads are becoming increasingly dynamic. Think for instance of smartphones, which need to be both energy-efficient when standby and high-performance to run games or encode HD video in real-time. The current de-facto standard is to use two different cores and juggle applications between them. What if you could do this with a single core, removing the migration overhead?
- Education: the ρ-VEX is written entirely by students. We have had over 20 MSc and PhD students work on the project, targeting everything from architecture design to peripherals and from compilers to applications. The processor is also used in various lab courses at the TU Delft. If you’re a professor and this sounds interesting to you, please don’t hesitate to contact us!
- Research: the ρ-VEX is designed for research. It can be easily modified to do experiments – not only relating to reconfiguration, but VLIW architecture in general. We are collaborating with several universities and companies, for instance through the ALMARVI project, and have open-sourced a large portion of the project for any interested student or researcher!
What can the ρ-VEX do for you?
An open-source reconfigurable VLIW soft-core processor.
The current ρ-VEX release comes with the VHDL source files of the processor and peripherals, a GCC-like compiler (Open64), debug support software and hardware, and an architecture simulator. It is intended primarily for experimentation: if you would like to learn about VLIW architecture and want to hack away, or simply need a bit more DSP-like processing power for your project than a MicroBlaze can give you, this is the project for you. If you’re looking for a mission-critical processor however, perhaps not – we mainly focus our time on research and development, and thus there will be bugs. The compiler and processor are very stable though: stable enough to build and run a basic version of headless Linux.
You can find releases and other files here. You can only download if you have an e-mail address from an educational institution; contact us otherwise.
Read how to get started with the current release of the ρ-VEX processor.
Read how to get in touch with us, to get more information about the processor or the project in general, or to discuss possibilities for collaboration.